Kevin O'Buckley of Marvell tells EE Times, “We’ve been able to achieve on average 40 percent lower power for a given design point and performance point. We’ve been able to achieve 40 percent greater integration, mostly measured as die area shrink, which can be used either to pack in more performance in a given die area or in some cases, lower costs.” Marvell finds, "TSMC’s 5nm technology which delivers approximately 20 percent faster speed or 40 percent power reduction compared to the previous 7nm generation."

Moore's Law is slowing down, but how much? Far too many claims are made based on inappropriate comparisons. O'Buckley answered me, "40% lower power was by taking some key designs in N7 and moving them to N5 at fixed performance (and lower voltage.)" (There is an immediate process, TSMC's N7+, which uses EUV.)

O'Buckley is a senior chip engineer working directly with the foundry. This is probably the best simple estimate of the improvement going from 7 nm (DUV) to 5 nm (EUV,) There are dozens of different factors in the performance of any given chip, including the quality of the design. Results will differ.

Only TSMC, Samsung, and Intel are using the Dutch ASML EUV machines, essential for all chips at 5 nm and below. The U.S. is blocking ASML from shipping EUV to SMIC or anyone else in China. For now, that means a hard stop in performance improvements at the first generation (DUV) 7 nm level. 

9 out of 10 applications are served just fine with the 14 nm and soon 7 nm (DUV) processes available in China. It may require 2 chips and tricky engineering to deliver the same performance of the more advanced chips, however. That adds $5-$30 to the cost and requires space, power, and cooling. 

A 5G radio can work fine with 12 nm chips. It sells for $2,000-$25,000, so the extra cost is a very minor factor.

An advanced 5G phone, however, requires the most advanced chips. If the U.S. continues to block Huawei from TSMC & Samsung, it will not be able to produce the best phones.

China has unlimited funding for a crash program to develop its own EUV and get around the U.S. blockade. 

Marvell and TSMC Collaborate to Deliver Industry’s Most Advanced Data Infrastructure Portfolio on 5nm Technology

SANTA CLARA, Calif. – August 25, 2020 – Marvell (NASDAQ: MRVL), a leading provider of data infrastructure semiconductor solutions, today announced an extension of their long term partnership with TSMC (TWSE: 2330; NYSE:TSM), the world’s largest dedicated semiconductor foundry, to deliver a comprehensive silicon portfolio for the data infrastructure market leveraging the industry’s most advanced 5 nanometer (nm) process technology. Next-generation infrastructure has never been more critical to the global economy. It’s what’s keeping the world connected, businesses running and information flowing. With this collaboration, Marvell and TSMC are advancing the essential technology underpinning this infrastructure to provide the storage, bandwidth, speed, and intelligence that tomorrow’s digital economy demands – with the added customer benefit of significant energy efficiency. Built in partnership with TSMC on the most advanced process technology currently in volume production, Marvell’s new 5nm portfolio will enable leading-edge silicon innovation for the infrastructure market.

Marvell’s breakthrough 5nm portfolio will provide the essential high-performance compute, networking and security technology required to advance infrastructure development for a multitude of end-market applications. Marvell’s Ethernet connectivity solutions enable high-performance, low-power network connectivity, optimized for applications that span cloud data centers to the harsh environment of the automotive market. Marvell’s OCTEON® platform is the industry’s leading Arm-based high-performance compute architecture for embedded infrastructure applications targeting a wide variety of wired and wireless networking equipment including switches, routers, secure gateways, firewalls, and network monitoring solutions. OCTEON is the world’s most widely deployed data processing unit (DPU) for data-center scale computing and enables a multitude of acceleration and offload capabilities, including Smart NICs and security accelerators. Featuring optimized and customized 5G processing and baseband capabilities, Marvell’s OCTEON Fusion® platform is pushing the boundaries of wireless network infrastructure.

With multiple designs already under contract for its 5nm portfolio, Marvell is developing solutions across the carrier, enterprise, automotive, and data center markets with first products sampling by the end of next year. This marks a significant milestone for the infrastructure industry as the process node cadence now closely follows that of the consumer and high-performance market. This joint development positions Marvell for multi-generational leadership in data infrastructure technology. These advanced systems based on Marvell’s leading technology platform will set a new bar for power and performance for the industry.

Behind Marvell’s entire 5nm solution set is the company’s industry-leading IP portfolio that covers the full spectrum of infrastructure requirements including high-speed SerDes up to 112Gbps long-reach, processor subsystems, encryption engines, system-on-chip fabrics, chip-to-chip interconnects, and a variety of physical layer interfaces. These technologies and more are all in development now on TSMC’s N5P process, an enhanced version of TSMC’s 5nm technology which delivers approximately 20 percent faster speed or 40 percent power reduction compared to the previous 7nm generation.

This rich collaboration between the two companies extends beyond 5nm to provide a reliable and long-term roadmap for Marvell’s customers.

“We are proud to partner with Marvell to serve the data infrastructure market with cutting-edge silicon, and are committed to supporting their growing needs in development, quality, supply and capacity," said Dr. Kevin Zhang, Senior Vice President of Business Development at TSMC. “In the 5G era, more applications than ever are demanding the most advanced silicon technology we can provide. We look forward to collaborating with Marvell to meet these demands with our combined design and process expertise and extend our long history of partnership to the 5nm generation and beyond."

“Now is the time to invest in data infrastructure – the world is relying on us – and our customers are depending on us," said Raghib Hussain, Chief Strategy Officer and Executive Vice President of the Networking and Processors Group at Marvell. “TSMC’s 5nm process provides world-class power, performance and gate density – and it’s critical for the demands of the leading companies in the world in cloud, 5G, enterprise, and automotive. We’re thrilled to have a strategic partner like TSMC to help us continue to push the boundaries of innovation possibilities."