Kevin O'Buckley of Marvell tells EE Times, “We’ve been able to achieve on average 40 percent lower power for a given design point and performance point. We’ve been able to achieve 40 percent greater integration, mostly measured as die area shrink, which can be used either to pack in more performance in a given die area or in some cases, lower costs.” Marvell finds, "TSMC’s 5nm technology which delivers approximately 20 percent faster speed or 40 percent power reduction compared to the previous 7nm generation."
Moore's Law is slowing down, but how much? Far too many claims are made based on inappropriate comparisons. O'Buckley answered me, "40% lower power was by taking some key designs in N7 and moving them to N5 at fixed performance (and lower voltage.)" (There is an immediate process, TSMC's N7+, which uses EUV.)